1. Field of the Invention
The present invention relates to a method of producing a multi-layered wiring board and more particularly to the method of producing a multi-layered wiring board by laminating serially conductor layers and insulating layers.
2. Description of the Background Art
A finer pattern and a multi-layered structure have been employed rapidly in printed wiring boards for mounting semiconductor devices as the electronic appliances have become smaller in size and weight and higher in operation speed and function. Via-holes that establish electric conduction between upper and lower circuits at arbitrary positions are not easily formed in multi-layered wiring structures on press laminated boards. For this reason, a build-up system that laminates serially and alternately insulating layers and conductor layers to form a multi-layered wiring board has been employed instead.
The multi-layered wiring board by the build-up system has generally the structure in which via-holes of upper layers and via-holes of lower layers do not overlap with one another. To achieve a higher signal speed, however, a circuit pattern must be as short as possible, and a “via-on-via structure”, in which the via-holes of the upper layers are stacked on the via-holes of the lower layers, has drawn an increasing attention.
A process for forming the via-holes is described in the following reference, for example:    “High Density Build-up Technology for Flip Chip Application”, Mottoi Asai, p 200, IEMT/IMC Proceedings 1999
This technology uses a photo via-hole process. The conventional formation method of via-on-via by the build-up system will be explained with reference to this technology.
FIG. 6 shows a basic shape of a core substrate 3 for forming the multi-layered wires. A wiring pattern 20a having lines 40 and lands 50 as a first conductor layer is formed beforehand by photolithography or like means on the core substrate 3. In the example shown, a land (via-hole) pitch is 800 μm and a land diameter (LD) is 250 μm. Two lines are extended at 100 μm L/S (line/space) between the lands.
FIG. 8 shows the conventional process for forming via-on-via on the core substrate 3. In the drawing, reference numeral 1 denotes a first insulating layer having a photosensitive negative type resist, for example. Reference numeral 11 denotes an insulating layer pattern formed when the first insulating layer 1 is exposed and developed. Reference numeral 8 denotes a via for holding electric conduction between upper layer lands and lower layer lands. Reference numeral 60 denotes a photo-mask formed by vacuum depositing a metal such as Cr to portions corresponding to lands represented by 50. An arrow 70 represents ultraviolet rays that are used for exposure, and reference numeral 80 denotes a via-hole.
Suffixes a, b, c and d will be used to identify the first, second, third and fourth layers when a member having the same function is formed in a plurality of layers.
In the first step 1, a first insulating layer 1a of the first layer is spin-coated uniformly to a thickness of 5 to 70 μm on the core substrate 3, for example. Pre-baking is then conducted at 70 to 150° C. to evaporate away an excessive solvent contained in the first insulating layer 1a. 
In the step 2, ultraviolet rays are irradiated to expose the first insulating layer 1a with a photo-mask 60a. Reaction components such as acids and radicals occur at the portions irradiated by the ultra-violet rays 70a, forming a cross-linked structures.
In the step 3, development is conducted. When the first insulating layer 1a is washed with a developing solution, the portions not irradiated with the ultra-violet rays 70a are dissolved away. In consequence, an insulating layer pattern 11a inclusive of the via-holes 80a is formed.
In the step 4, an electrically conductive resin is buried into each via-hole to form a via 8a. A second layer wiring pattern 20b is formed on this via 8a by a semi-additive process, for example. The semi-additive process is the method of forming an electrolytic plating by applying electroless copper plating to the entire surface, forming a wiring pattern by using a plating resist and growing electroplating on only the wiring portion by using the exposed chemical copper plating film as an electrode.
In the step 5, the first insulating layer 1b as the second layer is formed uniformly by the same method as that, of the step 1, and pre-baking is conducted, when necessary. In the step 6, the ultra-violet rays 70b are irradiated for exposure with the photo-mask 60b in the same way as in the step 2. In the step 7, the first insulating layer 1b as the second layer is developed in the same way as in the step 3, forming the via-holes 80b of the second layer. In the step 8, the electrically conductive resin is buried in the same way as in the step 4 to form a via 8b. Electroless plating and electroplating are carried out serially to complete the wiring pattern 20c of the third layer.
A series of the process steps described above form the via-on-via structure. The size of the via-holes or the lands is the same for each layer, and two lines are formed between the land and the land.
The process described above uses photolithography for forming the via-holes, but it is also possible to form the via-holes in the insulating layer 1 by irradiating an excimer laser or a YAG laser without using the mask.
As the semiconductor devices mounted onto the multi-layered wiring board are required to possess higher functions, the number of input/output pins provided to the semiconductor devices and eventually, the number of lines necessary for a wiring pattern, increases drastically.
The number of lines that can be extended between lands becomes greater when the size of via-holes (or lands) is smaller if the pitch between the via-holes (or the lands) is constant. Therefore, many attempts have been made to reduce the size of the via-holes. The conventional method of forming the via-holes involves the resolution limit of a photolithography process or the restriction by an irradiation diameter of a laser beam spot, and never satisfactorily miniaturize the via-holes. In consequence, a greater number of lamination is required for the multi-layered wiring board and the production cost soars.